https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125183
Bug ID: 125183
Summary: Odd SSE register allocation
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Keywords: ra
Severity: minor
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: roger at nextmovesoftware dot com
Target Milestone: ---
Target: x86_64-*-*
GCC currently makes a strange choice of register allocation in the following
(tiny) example:
typedef char v16qi __attribute__ ((vector_size(16)));
v16qi slt0(v16qi x) { return x < 0; }
where with -O2 -mavx2, recent GCC generates:
slt0: vmovdqa xmm1, xmm0
vpxor xmm0, xmm0, xmm0
vpcmpgtb xmm0, xmm0, xmm1
ret
where GCC 8.x and earlier, and recent clang/llvm generate:
slt0: vpxor xmm1, xmm1, xmm1
vpcmpgtb xmm0, xmm1, xmm0
ret
Is there anything the i386 backend can do to help the register allocator make a
better choice, or is this something that needs to be cleaned up with a
peephole2? My apologies if this is a FAQ.
