[Bug middle-end/96633] missed optimization?

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96633

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
For aarch64:

Current we have:
```
        and     w0, w0, 1
        csel    w0, w0, wzr, cc
```

LLVM gets:
```
        cset    w9, lo
        and     w0, w9, w8
```

that is
```
(set (reg:SI 0 x0)
    (if_then_else:SI (ltu (reg:CC 66 cc)
            (const_int 0 [0]))
        (and:SI (subreg:SI (reg:DI 107 [ _2 ]) 0)
            (const_int 1 [0x1]))
        (const_int 0 [0])))
```

Since STORE_FLAG_VALUE is 1. This can be converted into:
```
(set (reg:SI 0 x0)
     (and:SI (subreg:SI (reg:DI 107 [ _2 ]) 0)
             (ltu (reg:CC 66 cc) (const_int 0 [0]))))
```

The cset version is slightly better because it has no dependencies.