[Bug target/121778] Improve rotation detection for RISC-V

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121778

--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <l...@gcc.gnu.org>:

https://gcc.gnu.org/g:d53f7ad85e8aefc6f0cdc0dd2f541db59d1a0cd2

commit r16-4084-gd53f7ad85e8aefc6f0cdc0dd2f541db59d1a0cd2
Author: Dusan Stojkovic <dusan.stojko...@rt-rk.com>
Date:   Wed Sep 24 15:11:58 2025 -0600

    [PATCH][PR target/121778] RISC-V: Improve rotation detection for RISC-V

    This patch splits the canonical sign-bit checking idiom
    into a 2-insn sequence when Zbb is available. Combine often normalizes
    (xor (lshr A, (W - 1)) 1) to (ge A, 0). For width W = bitsize (mode), the
    identity:

    (a << 1) | (a >= 0)  ==  (a << 1) | ((a >> (W - 1)) ^ 1)  ==  ROL1 (a) ^ 1

    lets us split:

    (ior:X (ashift:X A 1) (ge:X A 0))

    into:
      â  rotatert:X A, (W-1)
      â  xor:X        A, 1

            PR target/121778

    gcc/ChangeLog:

            * config/riscv/riscv.md: Add define_split pattern.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/pr121778-1.c: New test.
            * gcc.target/riscv/pr121778-2.c: New test.