https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93738
--- Comment #13 from Kishan Parmar <kishan at gcc dot gnu.org> ---
Big Endian Target
==================
(insn 10 9 11 2 (set (reg:SI 124)
(and:SI (lshiftrt:SI (subreg:SI (reg:DI 129 [ x+-4 ]) 4) (const_int 12
[0xc]))
(const_int 3840 [0xf00]))) 246 {*rotlsi3_mask}
(insn 13 11 14 2 (set (reg:SI 127)
(and:SI (reg:SI 125 [+-2 ])
(const_int -3841 [0xfffffffffffff0ff]))) 211 {andsi3_mask}
(insn 14 13 15 2 (set (reg:SI 128)
(ior:SI (reg:SI 127)
(reg:SI 124))) "../testcase/testcase.c":10:7 226 {*boolsi3}
Operand of 10 gets converted to below insn
(and:SI (subreg:SI (lshiftrt:DI (reg:DI 129 [ x+-4 ])
(const_int 12 [0xc])) 4)
(const_int 3840 [0xf00]))
And at end we are creating below final pattern which failed to match
(set (reg:SI 128)
(ior:SI (and:SI (reg:SI 125 [+-2 ])
(const_int -3841 [0xfffffffffffff0ff]))
(and:SI (subreg:SI (zero_extract:DI (reg:DI 129 [ x+-4 ])
(const_int 32 [0x20])
(const_int 20 [0x14])) 4)
(const_int 3840 [0xf00]))))
Failed to match this instruction:
(set (reg:SI 128)
(ior:SI (and:SI (reg:SI 125 [+-2 ])
(const_int -3841 [0xfffffffffffff0ff]))
(and:SI (subreg:SI (and:DI (lshiftrt:DI (reg:DI 129 [ x+-4 ])
(const_int 12 [0xc]))
(const_int 4294967295 [0xffffffff])) 4)
(const_int 3840 [0xf00]))))
Failed to match this instruction:
(set (reg:DI 127 [+-4 ])
(zero_extract:DI (reg:DI 129 [ x+-4 ])
(const_int 32 [0x20])
(const_int 20 [0x14])))
Successfully matched this instruction:
(set (reg:DI 127 [+-4 ])
(and:DI (lshiftrt:DI (reg:DI 129 [ x+-4 ])
(const_int 12 [0xc]))
(const_int 4294967295 [0xffffffff])))
Successfully matched this instruction:
(set (reg:SI 128)
(ior:SI (and:SI (reg:SI 125 [+-2 ])
(const_int -3841 [0xfffffffffffff0ff]))
(and:SI (subreg:SI (reg:DI 127 [+-4 ]) 4)
(const_int 3840 [0xf00]))))
allowing combination of insns 10, 13 and 14
original costs 4 + 4 + 4 = 12
replacement costs 4 + 4 = 8
deferring deletion of insn with uid = 10.
modifying insn i2 13: r127:DI=r129:DI 0>>0xc&0xffffffff
REG_DEAD r129:DI
deferring rescan insn with uid = 13.
modifying insn i3 14: r128:SI=r125:SI&0xfffffffffffff0ff|r127:DI#4&0xf00
Before r9-3594 scenario (gcc-8)
==============================
subreg:SI (reg:DI %r3) get converted to (reg:SI 3 %r3), since it is hard
register,
which can be simplified.
Later On,
(insn 10 9 11 2 (set (reg:SI 128)
(and:SI (lshiftrt:SI (reg:SI 3 %r3 [ x ])
(const_int 12 [0xc]))
(const_int 3840 [0xf00]))) 240 {*rotlsi3_mask}
(insn 13 11 14 2 (set (reg:SI 131)
(and:SI (reg:SI 129 [+-2 ])
(const_int -3841 [0xfffffffffffff0ff]))) 206 {andsi3_mask}
(insn 14 13 15 2 (set (reg:SI 132)
(ior:SI (reg:SI 131)
(reg:SI 128))) 220 {*boolsi3}
Trying 13, 10 -> 14:
13: r131:SI=r129:SI&0xfffffffffffff0ff
REG_DEAD r129:SI
10: r128:SI=%r3:SI 0>>0xc&0xf00
REG_DEAD %r3:DI
14: r132:SI=r131:SI|r128:SI
REG_DEAD r131:SI
REG_DEAD r128:SI
Successfully matched this instruction:
(set (reg:SI 132)
(ior:SI (and:SI (reg:SI 129 [+-2 ])
(const_int -3841 [0xfffffffffffff0ff]))
(and:SI (lshiftrt:SI (reg:SI 3 %r3 [ x ])
(const_int 12 [0xc]))
(const_int 3840 [0xf00]))))
