https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119100
--- Comment #12 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <l...@gcc.gnu.org>: https://gcc.gnu.org/g:99a3c71db6edb8dc8c426cb2530f9cefbb5bfc9e commit r16-2230-g99a3c71db6edb8dc8c426cb2530f9cefbb5bfc9e Author: Paul-Antoine Arras <par...@baylibre.com> Date: Mon Jul 14 06:10:44 2025 -0600 [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100] This pattern enables the combine pass (or late-combine, depending on the case) to merge a float_extend'ed vec_duplicate into a plus-mult or minus-mult RTL instruction. Before this patch, we have three instructions, e.g.: fcvt.s.h fa5,fa5 vfmv.v.f v24,fa5 vfmadd.vv v8,v24,v16 After, we get only one: vfwmacc.vf v8,fa5,v16 PR target/119100 gcc/ChangeLog: * config/riscv/autovec-opt.md (*vfwmacc_vf_<mode>): New pattern to handle both vfwmacc and vfwmsac. (*extend_vf_<mode>): New pattern that serves as an intermediate combine step. * config/riscv/vector-iterators.md (vsubel): New mode attribute. This is just the lower-case version of VSUBEL. * config/riscv/vector.md (@pred_widen_mul_<optab><mode>_scalar): Reorder and swap operands to match the RTL emitted by expand, i.e. first float_extend then vec_duplicate. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfwmacc and vfwmsac. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise. Also check for fcvt and vfmv. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Add vfwmacc and vfwmsac. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise. Also check for fcvt and vfmv. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h: Add support for widening variants. * gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h: New test helper. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c: New test.
