[Bug target/120828] New: [16 Regression] Unrecognized insn after recent RISC-V change for .vf support

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120828

            Bug ID: 120828
           Summary: [16 Regression] Unrecognized insn after recent RISC-V
                    change for .vf support
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: law at gcc dot gnu.org
  Target Milestone: ---

This is marginally reduced from rvv/base/bug-5.c.  Compile with -O2
-march=rv64gcv -mabi=lp64d to trigger an unrecognized insn:



#include "riscv_vector.h"

vfloat32m1_t frob()
{
  vfloat32m1_t vb;
  vfloat32m1_t vc;
  vfloat32m1_t vd = __riscv_vfmsub_vf_f32m1 (vb, 1.0f, vc, 1);
  return vd;
}

j.c:12:1: error: unrecognizable insn:
   12 | }
      | ^
(insn 8 7 12 2 (set (reg/v:RVVM1SF 136 [ <retval> ])
        (if_then_else:RVVM1SF (unspec:RVVMF32BI [
                    (const_vector:RVVMF32BI repeat [
                            (const_int 1 [0x1])
                        ])
                    (const_int 1 [0x1])
                    (const_int 2 [0x2]) repeated x2
                    (const_int 0 [0])
                    (const_int 7 [0x7])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                    (reg:SI 69 frm)
                ] UNSPEC_VPREDICATE)
            (minus:RVVM1SF (mult:RVVM1SF (vec_duplicate:RVVM1SF (reg/v:RVVM1SF
134 [ vb ]))
                    (reg:SF 137))
                (reg/v:RVVM1SF 135 [ vc ]))
            (reg/v:RVVM1SF 134 [ vb ]))) "j.c":10:21 -1
     (nil))
during RTL pass: vregs

Note the failure is in the .vregs pass indicating the initial RTL generation is
incorrect.