[Bug target/120811] New: RISC-V: missed load offset

[parras at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120811

            Bug ID: 120811
           Summary: RISC-V: missed load offset
           Product: gcc
           Version: 15.1.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: parras at gcc dot gnu.org
  Target Milestone: ---

Created attachment 61701
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=61701&action=edit
Source reduced from 507.cactuBSSN

https://godbolt.org/z/1d94cTGYE

This is reduced from 507.cactuBSSN. The assembly shows (lines 67-68) the
following sequence:

        addi    t1,t1,1
        ld      t1,0(t1)

Instead of using the 12-bit sign-extended immediate of ld, GCC emits an extra
addi.
This, and similar patterns, happen many times within the original benchmark.