[Bug target/112431] RISC-V GCC-15 feature: Support register overlap on widen RVV instructions

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112431

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #16 from Jeffrey A. Law <law at gcc dot gnu.org> ---
We get pretty efficient code now.  No spills.  Appears to have been that way
since the gcc-14 release.