https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120469
Bug ID: 120469
Summary: [SH] Delay slot optimization opportunity missed with
atomic writes
Product: gcc
Version: 15.1.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: paul at crapouillou dot net
Target Milestone: ---
Given the following code:
#include <stdatomic.h>
unsigned int val;
void reset_val(void) {
if (TEST_ATOMIC)
atomic_store(&val, 0);
else
val = 0;
}
When compiling with TEST_ATOMIC==0 for SH4 (-Os -fno-PIC -fomit-frame-pointer
-m4-single), the following code is generated:
_reset_val:
mov.l .L2,r1
mov #0,r2
rts
mov.l r2,@r1
.L2:
.long _val
_val:
.zero 4
When compiling with TEST_ATOMIC==1, the second mov.l does not fill the delay
slot:
_reset_val:
mov.l .L2,r1
mov #0,r2
mov.l r2,@r1
rts
nop
.L2:
.long _val
_val:
.zero 4
