https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70557
--- Comment #14 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <l...@gcc.gnu.org>: https://gcc.gnu.org/g:c77085970ec98916e12e079a5a9d9530b86aae71 commit r16-824-gc77085970ec98916e12e079a5a9d9530b86aae71 Author: Siarhei Volkau <lis8...@gmail.com> Date: Thu May 22 08:52:17 2025 -0600 [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32 Patch is originally from Siarhei Volkau <lis8...@gmail.com>. RISC-V has a zero register (x0) which we can use to store zero into memory without loading the constant into a distinct register. Adjust the constraints of the 32-bit movdi_32bit pattern to recognize that we can store 0.0 into memory using x0 as the source register. This patch only affects RISC-V. It has been regression tested on riscv64-elf. Jeff has also tested this in his tester (riscv64-elf and riscv32-elf) with no regressions. PR target/70557 gcc/ * config/riscv/riscv.md (movdi_32bit): Add "J" constraint to allow storing 0 directly to memory.
