https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120090
--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Before we could do this
```
Trying 15 -> 16:
15: {r121:SI=zero_extend(unspec[[r98:SI],r112:V8HI,0]
157);r115:QI=unspec[[r98:SI],r112:V8HI,0] 157;}
REG_DEAD r112:V8HI
REG_DEAD r98:SI
16: r120:DI=zero_extend(r121:SI)
REG_DEAD r121:SI
Successfully matched this instruction:
(parallel [
(set (reg:DI 120 [ _6 ])
(zero_extend:DI (unspec:QI [
(mem:V8HI (reg/f:SI 98 [ pi128.0_1 ]) [0 *pi128.0_1+0
S16 A128])
(reg:V8HI 112 [ _18 ])
(const_int 0 [0])
] UNSPEC_UNSIGNED_PCMP)))
(set (reg:QI 115)
(unspec:QI [
(mem:V8HI (reg/f:SI 98 [ pi128.0_1 ]) [0 *pi128.0_1+0 S16
A128])
(reg:V8HI 112 [ _18 ])
(const_int 0 [0])
] UNSPEC_UNSIGNED_PCMP))
])
allowing combination of insns 15 and 16
original costs 0 + 4 = 0
replacement cost 0
deferring deletion of insn with uid = 15.
deferring deletion of insn with uid = 15.
modifying insn i3 16: {r120:DI=zero_extend(unspec[[r98:SI],r112:V8HI,0]
157);r115:QI=unspec[[r98:SI],r112:V8HI,0] 157;}
REG_DEAD r98:SI
REG_DEAD r112:V8HI
deferring rescan insn with uid = 16.
```
But after it combine does not and does not say why though.
