[Bug target/120036] [16 Regression] ICE on highway-1.2.0: during RTL pass: rrvl: in gen_rtx_SUBREG, at emit-rtl.cc:1032

[slyfox at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120036

Sergei Trofimovich <slyfox at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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            Version|15.0                        |16.0
                 CC|                            |hjl.tools at gmail dot com

--- Comment #1 from Sergei Trofimovich <slyfox at gcc dot gnu.org> ---
Bisect says r16-271-gd1cada7481420a exposed this failure

  commit d1cada7481420a23fbec525548ef5bdf64839a34 (HEAD)
  Author: H.J. Lu <hjl.to...@gmail.com>
  Date:   Fri Nov 29 18:22:14 2024 +0800

    x86: Add a pass to remove redundant all 0s/1s vector load