https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114277
--- Comment #10 from Jeffrey A. Law <law at gcc dot gnu.org> --- So on the RISC-V specific side of this we will need a bit of work and all things that would help address some of the weaknesses in utilization of the zicond extension. First, for the comparison in the conditional move. We need to support subword sized operands. I've wanted to do that for a while, but hadn't gotten around to it yet. It's pretty simple. Use riscv_extend_comparands to generate suitable RTL and force_reg to force the result into a register. Second, we need to support subword destinations, particularly SI on TARGET_64BIT. When the destination has a sub-word mode, we can instead use a word_mode temporary and a subreg-lowpart extraction at the end of the sequence. This is well understood and we use this idiom elsewhere in the risc-v port. Finally we need to adjust for subword operands in the true/false arms. Overall, not bad and definitely where this code should be going anyway. Just want to get it recorded in case I get swamped again and forget the path forward on this bz.
