https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116256
--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <l...@gcc.gnu.org>: https://gcc.gnu.org/g:1edd93fbaddce9b2938e2927014272fa621ade9c commit r15-7082-g1edd93fbaddce9b2938e2927014272fa621ade9c Author: Jeff Law <j...@ventanamicro.com> Date: Mon Jan 20 15:05:34 2025 -0700 [PR target/116256] Adjust expected output in a couple testcases I've had a long standing TODO to review the RISC-V testsuite regressions from enabling the late-combine pass (pr116256). I adjusted a few cases months ago, this adjusts a couple more were it looks like the right thing to do. All that's left after this are the vls/dup-? tests which regress in meaningful ways and I'm still investigating reasonable approaches to fix them (they play into the whole mvconst_internal pattern situation), late-combine isn't doing anything wrong. PR target/116256 gcc/testsuite * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Update expected output. * gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Likewise.
