https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118384
--- Comment #8 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The trunk branch has been updated by Richard Sandiford <rsand...@gcc.gnu.org>: https://gcc.gnu.org/g:8edf8b552313951cb4f2f97821ee4b3820c9506b commit r15-7074-g8edf8b552313951cb4f2f97821ee4b3820c9506b Author: Richard Sandiford <richard.sandif...@arm.com> Date: Mon Jan 20 19:52:31 2025 +0000 vect: Preserve OMP info for conditional stores [PR118384] OMP reductions are lowered into the form: idx = .OMP_SIMD_LANE (simuid, 0); ... oldval = D.anon[idx]; newval = oldval op ...; D.anon[idx] = newval; So if the scalar loop has a {0, +, 1} iv i, idx = i % vf. Despite this wraparound, the vectoriser pretends that the D.anon accesses are linear. It records the .OMP_SIMD_LANE's second argument (val) in the data_reference aux field (-1 - val) and then copies this to the stmt_vec_info simd_lane_access_p field (val + 1). vectorizable_load and vectorizable_store use simd_lane_access_p to detect accesses of this form and suppress the vector pointer increments that would be used for genuine linear accesses. The difference in this PR is that the reduction is conditional, and so the store back to D.anon is recognised as a conditional store pattern. simd_lane_access_p was not being copied across from the original stmt_vec_info to the pattern stmt_vec_info, meaning that it was vectorised as a normal linear store. gcc/ PR tree-optimization/118384 * tree-vectorizer.cc (vec_info::move_dr): Copy STMT_VINFO_SIMD_LANE_ACCESS_P. gcc/testsuite/ PR tree-optimization/118384 * gcc.target/aarch64/pr118384_1.c: New test. * gcc.target/aarch64/pr118384_2.c: Likewise.
