https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118533
Bug ID: 118533
Summary: [15 regression] bfloat16_scalar_*.c failures since
r15-1619-g3b9b8d6cfdf593
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: jskumari at gcc dot gnu.org
Target Milestone: ---
Since commit r15-1619-g3b9b8d6cfdf593 we see these regressions on
armv8l-linux-gnueabihf:
Running gcc:gcc.target/arm/arm.exp ...
FAIL: gcc.target/arm/bfloat16_scalar_1_1.c check-function-bodies bfloat_mov_mr
FAIL: gcc.target/arm/bfloat16_scalar_1_2.c check-function-bodies bfloat_mov_mr
FAIL: gcc.target/arm/bfloat16_scalar_2_1.c check-function-bodies bfloat_mov_mr
FAIL: gcc.target/arm/bfloat16_scalar_2_2.c check-function-bodies bfloat_mov_mr
FAIL: gcc.target/arm/bfloat16_scalar_3_1.c check-function-bodies bfloat_mov_mr
FAIL: gcc.target/arm/bfloat16_scalar_3_2.c check-function-bodies bfloat_mov_mr
All these failures are due to an extra ‘mov’ instruction.
The testcase is:
volatile bfloat16_t x;
register bfloat16 : "r" (y));
With the commit r15-1619-g3b9b8d6cfdf593, we see the following instructions:
ldrh r3, [sp , #6] @ __bf16
mov r4, r3 @ __bf16
Without the commit, we get:
ldrh r4, [sp, #6] @ __bf16
The input RTL for the IRA pass is:
set r114, mem(sp, offset)
set r4, r114
With patch, r114 gets assigned to r3 (scratch register) while without patch,
r114 gets assigned to r4.
The inline asm in the testcase associates variable 'y' with r4 (a callee-save
register). This is the reason we have a copy from r114 to r4 in the RTL:
set r4, r114
When computing the costs of the hard registers in assign_hard_reg(), the
cost of saving/restoring a callee-save register in prolog/epilog is
taken into consideration. The save/restore cost is taken into consideration
only if the hard register has not already been assigned to an allocno by IRA.
In this testcase, since RTL already has a reference to r4 (due to the inline
asm), r4 should be available for allocation by the IRA without being charged a
spill/restore cost.
If r4 is not charged the spill/restore cost, then it’s cost will be lesser than
the cost for r3, and IRA will assign r4 to r114.
The array allocated_hardreg_p[] specifies if a hard register has already been
allocated to an allocno. This array is updated whenever a register is assigned.
This array should also be updated if a hard reg is being used (due to inline
asm specifying a register for a local variable).
