https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118122
--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <l...@gcc.gnu.org>: https://gcc.gnu.org/g:64d31343d4676d8ceef9232dcd33824bc2eff330 commit r15-6470-g64d31343d4676d8ceef9232dcd33824bc2eff330 Author: Jeff Law <j...@ventanamicro.com> Date: Mon Dec 30 07:40:07 2024 -0700 [RISC-V][PR target/118122] Fix modes in recently added risc-v pattern The new pattern to optimize certain code sequences on RISC-V played things a bit fast and loose with modes -- some operands were using the ALLI iterator while the scratch used X and the split codegen used X. Naturally under the "right" circumstances this would trigger an ICE due to mismatched modes. This patch uses X consistently in that pattern. It also fixes some formatting nits. Tested in my tester, but waiting on the pre-commit verdict before moving forward. PR target/118122 gcc/ * config/riscv/riscv.md (lui_constraint<X:mode>_and_to_or): Use X iterator rather than ANYI consistently. Fix formatting. gcc/testsuite * gcc.target/riscv/pr118122.c: New test.
