[Bug tree-optimization/118037] New: missing unswitch loops with RISCV intrinsics

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118037

            Bug ID: 118037
           Summary: missing unswitch loops with RISCV intrinsics
           Product: gcc
           Version: 14.2.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: normal
          Priority: P3
         Component: tree-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pinskia at gcc dot gnu.org
                CC: daniel.kruegler at googlemail dot com,
                    liutong2020 at iscas dot ac.cn, unassigned at gcc dot 
gnu.org
  Target Milestone: ---
            Target: riscv

Created attachment 59863
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59863&action=edit
testcase

+++ This bug was initially created as a clone of Bug #118026 +++

$ riscv64-unknown-linux-gnu-g++ -march=rv64gcv -O3 <foo.cpp>

source file: https://godbolt.org/z/a6qsorrfn



GCC currently produces:
```
        vsetvli t4,zero,e64,m2,ta,ma
        vmv.v.i v2,0
        ble     a3,zero,.L6
        li      t1,0
        li      t3,0
.L7:
        bgt     a2,zero,.L5
        addiw   t3,t3,1
        add     t1,t1,a1
        bne     a3,t3,.L7
```


But that bgt should have been moved outside of the loop.  It corresponds to
`width > 0`. 

I tried to reduce it but we would move the condition out of the outer loop as
expected.