https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118026

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2024-12-13
     Ever confirmed|0                           |1

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
There are 2 issues with the source (I will file the not unswitching loop
seperately).

On the extra moves, it is due to pred_single_widen_add<mode> using early
clobber:
```
(define_insn "@pred_single_widen_add<mode>"
  [(set (match_operand:VWEXTF 0 "register_operand"                  "=&vr, 
&vr")
        (if_then_else:VWEXTF
          (unspec:<VM>
            [(match_operand:<VM> 1 "vector_mask_operand"          
"vmWc1,vmWc1")
             (match_operand 5 "vector_length_operand"              "   rK,  
rK")
             (match_operand 6 "const_int_operand"                  "    i,   
i")
             (match_operand 7 "const_int_operand"                  "    i,   
i")
             (match_operand 8 "const_int_operand"                  "    i,   
i")
             (match_operand 9 "const_int_operand"                  "    i,   
i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)
             (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
          (plus:VWEXTF
            (float_extend:VWEXTF
              (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,  
vr"))
            (match_operand:VWEXTF 3 "register_operand"             "   vr,  
vr"))
          (match_operand:VWEXTF 2 "vector_merge_operand"           "   vu,   
0")))]
  "TARGET_VECTOR"
  "vfwadd.wv\t%0,%3,%4%p1"
  [(set_attr "type" "vfwalu")
   (set_attr "mode" "<V_DOUBLE_TRUNC>")
   (set (attr "frm_mode")
        (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
```

I suspect it does not need an early clobber here since you need to match up
operand 2 to operand 0.

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