https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117974
--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> --- We need to split all insns since some of them are not the ultimate RVV instruction pattern that depend on VL/VTYPE. And I don't think the vsetvli should be keep close VLE, instead, They are redundant, I think the problem is VSETVLI PASS fail to eliminate them since look into the RTL IR before VSETVLI PASS: https://godbolt.org/z/WdrjoYj49 (reg:DI 15 a5 [orig:139 _31 ] [139]) vsetvli a5,a1,e32,m1,tu,ma vle32.v v2,0(a0) sub a1,a1,a5 sh2add a0,a5,a0 vfmacc.vv v1,v2,v2 vsetvli a5,a1,e32,m1,tu,ma --> redudant should be elided. beq a1,zero,.L12 vle32.v v2,0(a0) sub a1,a1,a5 sh2add a0,a5,a0 vfmacc.vv v1,v2,v2 vsetvli a5,a1,e32,m1,tu,ma --> redudant should be elided. beq a1,zero,.L12 vle32.v v2,0(a0) sub a1,a1,a5 sh2add a0,a5,a0 vfmacc.vv v1,v2,v2 vsetvli a5,a1,e32,m1,tu,ma --> redudant should be elided. beq a1,zero,.L12 vle32.v v2,0(a0) sub a1,a1,a5 sh2add a0,a5,a0 vfmacc.vv v1,v2,v2 bne a1,zero,.L3
