https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117878
--- Comment #7 from Li Pan <pan2.li at intel dot com> ---
This insn is introduced during reload when lra_constraints. There will be const
vector like:
(const_vector:V8QI [
(const_int 4 [0x4])
(const_int 12 [0xc])
(const_int 5 [0x5])
(const_int 13 [0xd])
(const_int 6 [0x6])
(const_int 14 [0xe])
(const_int 7 [0x7])
(const_int 15 [0xf])
])
then expand_const_vector tries to generate it by vid and shift. At last the
expand_binop_directly will gen the pattern and then emit this insn.
(set (reg:V8QI 223) (lshiftrt:V8QI (reg:V8QI 222) (const_int 1 [0x1])))
Not sure if my understanding is correct but it looks nothing wrong here?
By the way, the define_insn_and_split contains 3 parts, define_insn,
define_split and define_expand, the
483 (define_insn_and_split "<optab><mode>3"
matched the standard name lshiftrt<mode>3, thus the reload is able to generate
the standard name pattern here as I understand. That indicates we can change
the name of "<optab><mode>3" to something like "xxx_<optab><mode>3" if we
really don't need this standard name for riscv backend.
Any suggestion here?
#0 expand_binop_directly (icode=CODE_FOR_lshrv8qi3, mode=E_V8QImode,
binoptab=lshr_optab, op0=0x7ffff723edb0, op1=0x7ffff74094a0, target=0x0,
unsignedp=0, methods=OPTAB_DIRECT, last=0x7ffff7239a00)
at /home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/optabs
cc:1474
1455 create_output_operand (&ops[0], target, tmp_mode); // create
(reg:V8QI 223)
1456 create_input_operand (&ops[1], xop0, mode0);
1457 create_input_operand (&ops[2], xop1, mode1);
1458 pat = maybe_gen_insn (icode, 3, ops);
pat = (set (reg:V8QI 223) (lshiftrt:V8QI (reg:V8QI 222) (const_int 1
[0x1])))
...
1474 emit_insn (pat);
#1 0x00000000019bc0bf in expand_binop (mode=E_V8QImode, binoptab=lshr_optab,
op0=0x7ffff723edb0, op1=0x7ffff74094a0, target=0x0, unsignedp=0,
methods=OPTAB_DIRECT)
at /home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/optabs
cc:1545
#2 0x00000000019bb37e in expand_simple_binop (mode=E_V8QImode, code=LSHIFTRT,
op0=0x7ffff723edb0, op1=0x7ffff74094a0, target=0x0, unsignedp=0,
methods=OPTAB_DIRECT)
at /home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/optabs
cc:1267
#3 0x00000000022e3b82 in riscv_vector::expand_const_vector
(target=0x7ffff723ed98, src=0x7ffff72255f0)
at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/config/riscv/riscv-v
cc:1442
1426 else
1427 {
1428 /* Case 2: For example as below:
1429 { -4, 4, -4 + 1, 4 + 1, -4 + 2, 4 + 2, -4 + 3, 4
+ 3, }
1430 */
1431 rvv_builder v (builder mode (), builder npatterns
(), 1);
1432
1433 /* Step 1: Generate { a, b, a, b, } */
1434 for (unsigned int i = 0; i < v npatterns (); ++i)
1435 v quick_push (builder elt (i));
1436 rtx new_base = v build ();
1437
1438 /* Step 2: Generate tmp1 = VID >> LOG2 (NPATTERNS)
*/
1439 rtx shift_count
1440 = gen_int_mode (exact_log2 (builder npatterns ()),
1441 builder inner_mode ());
1442 rtx tmp1 = expand_simple_binop (builder mode (),
LSHIFTRT,
1443 vid, shift_count,
NULL_RTX,
1444 false, OPTAB_DIRECT);
#4 0x00000000022e4764 in riscv_vector::legitimize_move (dest=0x7ffff723ed98,
srcp=0x7fffffffd078)
at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/config/riscv/riscv-v
cc:1605
#5 0x000000000374f410 in gen_movv8qi (operand0=0x7ffff723ed98,
operand1=0x7ffff72255f0)
at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/config/riscv/vector
md:1426
1421 (define_expand "mov<mode>"
1422 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand")
1423 (match_operand:VLS_AVL_IMM 1 "general_operand"))]
1424 "TARGET_VECTOR"
1425 {
1426 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1427 DONE;
1428 })
#6 0x00000000013b960b in insn_gen_fn::operator()<rtx_def*, rtx_def*>
(this=0x5208248 <insn_data+1381896>)
at /home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/gcc/recog
h:469
#7 0x00000000015a2759 in emit_move_insn_1 (x=0x7ffff723ed98, y=0x7ffff72255f0)
at /home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/expr
cc:4580
(set x = (reg:V8QI 221)
y = (const_vector:V8QI [
(const_int 4 [0x4])
(const_int 12 [0xc])
(const_int 5 [0x5])
(const_int 13 [0xd])
(const_int 6 [0x6])
(const_int 14 [0xe])
(const_int 7 [0x7])
(const_int 15 [0xf])
]))
#8 0x00000000015a319e in emit_move_insn (x=0x7ffff723ed98, y=0x7ffff72255f0)
at /home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/expr
cc:4750
#9 0x00000000018e80a8 in lra_emit_move (x=0x7ffff723ed98, y=0x7ffff72255f0)
at /home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/lra
cc:509
(set x = (reg:V8QI 221)
y = (const_vector:V8QI [
(const_int 4 [0x4])
(const_int 12 [0xc])
(const_int 5 [0x5])
(const_int 13 [0xd])
(const_int 6 [0x6])
(const_int 14 [0xe])
(const_int 7 [0x7])
(const_int 15 [0xf])
]))
#10 0x0000000001904029 in curr_insn_transform (check_only_p=false)
at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/lra-constraints
cc:4746
4737 if (get_reload_reg (type, mode, old, goal_alt[i],
4738
&goal_alt_exclude_start_hard_regs[i],
4739 loc != curr_id->operand_loc[i],
4740 curr_static_id->operand_alternative
4741 [goal_alt_number * n_operands + i]
earlyclobber,
4742 "", &new_reg)
4743 && type != OP_OUT)
4744 {
4745 push_to_sequence (before);
4746 lra_emit_move (new_reg, old);
4747 before = get_insns ();
4748 end_sequence ();
4749 }
#11 0x0000000001906918 in lra_constraints (first_p=false) at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/lra-constraints
cc:5503
#12 0x00000000018ed5ab in lra (f=0x610cd40, verbose=5) at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/lra cc:2463
#13 0x0000000001890dc2 in do_reload () at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/ira cc:5977
#14 0x00000000018912e3 in (anonymous namespace)::pass_reload::execute
(this=0x5f83d20) at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/ira cc:6165
#15 0x0000000001a38d2d in execute_one_pass (pass=0x5f83d20) at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/passes cc:2659
#16 0x0000000001a39110 in execute_pass_list_1 (pass=0x5f83d20) at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/passes cc:2768
#17 0x0000000001a39141 in execute_pass_list_1 (pass=0x5f82990) at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/passes cc:2769
#18 0x0000000001a3919e in execute_pass_list (fn=0x7ffff7fbc270, pass=0x5f7def0)
at /home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/passes
cc:2779
#19 0x000000000146090c in cgraph_node::expand (this=0x7ffff742d660) at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/cgraphunit
cc:1857
#20 0x0000000001461161 in expand_all_functions () at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/ /gcc/cgraphunit
cc:2040
#21 0x0000000001461c9c in symbol_table::compile (this=0x7ffff7406000) at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/cgraphunit
cc:2416
#22 0x0000000001462142 in symbol_table::finalize_compilation_unit
(this=0x7ffff7406000) at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/cgraphunit
cc:2601
#23 0x0000000001bd424f in compile_file () at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/toplev cc:479
#24 0x0000000001bd78a1 in do_compile () at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/toplev cc:2208
#25 0x0000000001bd7d1f in toplev::main (this=0x7fffffffdce2, argc=20,
argv=0x7fffffffde28) at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/toplev cc:2368
#26 0x000000000444906f in main (argc=20, argv=0x7fffffffde28) at
/home/pli/gcc/444/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__//gcc/main cc:39
