[Bug middle-end/117838] New: IRA issues: The higher cost variable a is spilled for the lower cost variable conflict_a in improve_allocatuion()

[lili.cui at intel dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117838

            Bug ID: 117838
           Summary: IRA issues: The higher cost variable a is spilled for
                    the lower cost variable conflict_a in
                    improve_allocatuion()
           Product: gcc
           Version: 15.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: lili.cui at intel dot com
  Target Milestone: ---

Created attachment 59740
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59740&action=edit
testcase-dump-patch

testcase :         sqlite3-ok.i (in attachment, It is extracted from SQLite)
gcc version:       Fri Oct 18 2024 (aaa855fac0c7003d823b48fe4cc4b9ded9331a2b)
compile options : -std=c18 -m64 -S -o sqlite3.s -Ofast -march=x86-64-v3
sqlite3-ok.i -da

Function: sqlite3VdbeExec
variable a : pOp -> a5(r806, l0) cost=30495
variable conflict_a : nDepth -> a2737(r1214,l0) cost 1102


Pushing a5(r806,l0)(potential spill: pri=26, cost=30495)
Pushing a2737(r1214,l0: a2656(r1214,l2: a1251(r1214,l17)))(cost 1102)
Popping a5(r806,l0)  --         assign reg 40
Popping a2737(r1214,l0: a2656(r1214,l2: a1251(r1214,l17))) -- assign reg 38

Spilling a5r806 for a2737r1214
Assigning 40 to a2737r1214
a5(r806,l0)  -- assign memory

It was introduced by the following commit:

commit 037cc0b4a6646cc86549247a3590215ebd5c4c43
Author: Richard Sandiford <richard.sandif...@arm.com>
Date:   Mon Jan 10 14:47:09 2022 +0000

    ira: Handle "soft" conflicts between cap and non-cap allocnos


I created a patch (in attachment) to drop the issue code, there is no
regression on graviton 3 and SPR with speccpu2017.