https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109279
--- Comment #22 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <l...@gcc.gnu.org>: https://gcc.gnu.org/g:df2e832c90fe0915c0ab89e5c115bd0c6536c833 commit r15-5602-gdf2e832c90fe0915c0ab89e5c115bd0c6536c833 Author: Jeff Law <j...@ventanamicro.com> Date: Fri Nov 22 16:11:03 2024 -0700 [RISC-V][PR target/109279] Improve RISC-V constant synthesis This is a small improvement to the constant synthesis code to capture a case appended to PR 109279. The case in question has the property that the high 32 bits have the value one less than the low 32 bits and the highest bit in two low 32 bits is on. The example used in BZ is 0xcccccccccccccccd which comes up computing N/10. When we construct a constant with bit 31 on, it gets implicitly sign extended. So something like 0xcccccccd when constructed would generate 0xffffffffcccccccd. The low bits are precisely what we want and the high bits are a "-1". Both properties are useful. We left shift that value by 32 positions into a temporary and add that temporary to the original value. Concretely: 0xffffffffcccccccd + 0xcccccccd00000000 ------------------ 0xcccccccccccccccd Tested in my tester on rv32 and rv64, waiting on the pre-commit tester to do its thing. PR target/109279 gcc/ * config/riscv/riscv.cc (riscv_build_integer): Handle another 64-bit synthesis where high half is one less than the low half and the 32-bit sign bit is on. gcc/testsuite/ * gcc.target/riscv/synthesis-16.c: New test.
