https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117718
--- Comment #5 from Steven Munroe <munroesj at gcc dot gnu.org> --- (In reply to Michael Meissner from comment #3) > No, the issue is with DQ addressing (i.e. vector load/store with offset), we > can't guarantee that the external address will be properly aligned with the > bottom 4 bits must be set to 0. The specific case I seeing is loading const vectors from .rodata. These are always quadword aligned. The compiler should know this as the offset is .TOC (R2) relative. That has to be case of -mcpu=power8 otherwise it could not use lvx. So it seems reasonable to assume that this is also true for P9/P10.
