[Bug target/117603] RISC-V: testsuite: Architecture string mutation is not robust

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117603

--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Dimitar Dimitrov <dimi...@gcc.gnu.org>:

https://gcc.gnu.org/g:eeff504238aeb4a9a20a9e445307b6773adb6f01

commit r15-5591-geeff504238aeb4a9a20a9e445307b6773adb6f01
Author: Dimitar Dimitrov <dimi...@dinux.eu>
Date:   Sat Nov 16 09:57:31 2024 +0200

    testsuite: RISC-V: Fix vector flags handling [PR117603]

    The DejaGnu routine "riscv_get_arch" fails to infer the correct
    architecture string when GCC is built for RV32EC.  This causes invalid
    architecture string to be produced by "add_options_for_riscv_v":
      xgcc: error: '-march=rv32cv': first ISA subset must be 'e', 'i' or 'g'

    Fix by adding the E base ISA variant to the list of possible architecture
    modifiers.

    Also, the V extension is added to the machine string without checking
    whether dependent extensions are available.  This results in errors when
    GCC is built for RV32EC:
      Executing on host: .../xgcc ... -march=rv32ecv ...
      cc1: error: ILP32E ABI does not support the 'D' extension
      cc1: sorry, unimplemented: Currently the 'V' implementation requires the
'M' extension

    Fix by disabling vector tests for RISC-V if V extension cannot be added
    to current architecture.

    Tested riscv32-none-elf for -march=rv32ec using GNU simulator.  Most of
    the remaining failures are due to explicit addition of vector options,
    yet missing "dg-require-effective-target riscv_v_ok":

                    === gcc Summary ===

     # of expected passes            211958
     # of unexpected failures        1826
     # of expected failures          1059
     # of unresolved testcases       5209
     # of unsupported tests          15513

    Ensured riscv64-unknown-linux-gnu tested with qemu has no new passing or
    failing tests, before and after applying this patch:

     Running target riscv-sim/-march=rv64imafdc/-mabi=lp64d/-mcmodel=medlow
     ...
                    === gcc Summary ===

     # of expected passes            237209
     # of unexpected failures        335
     # of expected failures          1670
     # of unresolved testcases       43
     # of unsupported tests          16767

            PR target/117603

    gcc/testsuite/ChangeLog:

            * lib/target-supports.exp (riscv_get_arch): Add comment about
            function purpose.  Add E ISA to list of possible
            modifiers.
            (check_vect_support_and_set_flags): Do not advertise vector
            support if V extension cannot be enabled.

    Signed-off-by: Dimitar Dimitrov <dimi...@dinux.eu>