[Bug target/117218] New: Miscompilation: A possible miscompilation triggered by the `__riscv_vcreate_v_u32m1x2` RVV intrinsic in GCC 14

[yibohe at pku dot edu.cn via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117218

            Bug ID: 117218
           Summary: Miscompilation: A possible miscompilation triggered by
                    the `__riscv_vcreate_v_u32m1x2` RVV intrinsic in GCC
                    14
           Product: gcc
           Version: 14.2.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: yibohe at pku dot edu.cn
  Target Milestone: ---

Link to the Compiler Explorer: https://godbolt.org/z/4bTcosera

For the following code with rvv intrinsics, there seems to be a miscompilation:
```
#include <riscv_vector.h>
int printf(const char *, ...);
int8_t data_mask[5]; uint32_t data_load_1[5]; uint32_t data_load_2[5]; 
int32_t data_load_3[5]; float data_load_4[5]; uint32_t data_store_vreg_3[5];

int main(){
  int8_t tmp_mask[5] = {0, 1, 0, 1, 1, }; for (int i = 0; i < 5; ++i) {
data_mask[i] = tmp_mask[i]; }
  uint32_t tmp_1[5] = {4271425586u, 1923065272u, 385778631u, 2492204083u,
837690518u, }; for (int i = 0; i < 5; ++i) { data_load_1[i] = tmp_1[i]; }
  uint32_t tmp_2[5] = {1570315145u, 2764202118u, 700162945u, 911905654u,
1782991139u, }; for (int i = 0; i < 5; ++i) { data_load_2[i] = tmp_2[i]; }
  int32_t tmp_3[5] = {517111323, 698334434, 790501285, -527885415, 1557147356,
}; for (int i = 0; i < 5; ++i) { data_load_3[i] = tmp_3[i]; }
  int8_t* heap_mask = data_mask; uint32_t* heap_load_1 = data_load_1; 
  uint32_t* heap_load_2 = data_load_2; uint32_t* heap_store_vreg_3 =
data_store_vreg_3;
  int placeholder0 = 5;
  for (size_t vl; placeholder0 > 0; placeholder0 -= vl){
    vl = __riscv_vsetvl_e32m1(placeholder0);
    vint8mf4_t vec_value_0= __riscv_vle8_v_i8mf4(heap_mask, vl);
    vbool32_t vmask= __riscv_vmseq_vx_i8mf4_b32(vec_value_0, 1, vl);
    vuint32m1_t vreg_memory_1 = __riscv_vlse32_v_u32m1(heap_load_1, 1, vl);
    vuint32m1_t vreg_memory_2 = __riscv_vle32_v_u32m1_m(vmask, heap_load_2,
vl);
    vuint32m1_t vreg_2 = __riscv_vrsub_vx_u32m1(vreg_memory_1, 4198250387u,
vl);
    vuint32m1x2_t vreg_3 = __riscv_vcreate_v_u32m1x2(vreg_2, vreg_memory_2);
        __riscv_vsseg2e32_v_u32m1x2(heap_store_vreg_3, vreg_3, vl);
    heap_mask += vl; heap_load_1 += vl; heap_load_2 += vl; heap_store_vreg_3 +=
vl;
  }
  for(int i=0; i<5; ++i) { if(data_mask[i]) printf("%x ",
data_store_vreg_3[i]); else printf("0 ");} printf("\n");
  return 0;
}
```

$riscv64-unknown-elf-gcc --version
riscv64-unknown-elf-gcc () 14.2.0
Copyright (C) 2024 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$qemu-riscv64 --version
qemu-riscv64 version 9.1.0
Copyright (c) 2003-2024 Fabrice Bellard and the QEMU Project developers

$riscv64-unknown-elf-gcc -march=rv64gcv_zvfh -mabi=lp64d -Wno-psabi -static -O0
1.c -o a.out && qemu-riscv64 a.out
$0 0 0 a4c26086 c84e12fd 
$riscv64-unknown-elf-gcc -march=rv64gcv_zvfh -mabi=lp64d -Wno-psabi -static -O3
1.c -o a.out && qemu-riscv64 a.out
$0 fe98c832 0 a4c26086 c84e12fd