https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109498
--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The trunk branch has been updated by Richard Sandiford <rsand...@gcc.gnu.org>: https://gcc.gnu.org/g:c94adf02d31028a25bb7b20ec77aade9d502430b commit r15-4174-gc94adf02d31028a25bb7b20ec77aade9d502430b Author: Soumya AR <soum...@nvidia.com> Date: Tue Oct 8 14:37:24 2024 +0100 aarch64: Expand CTZ to RBIT + CLZ for SVE [PR109498] Currently, we vectorize CTZ for SVE by using the following operation: .CTZ (X) = (PREC - 1) - .CLZ (X & -X) Instead, this patch expands CTZ to RBIT + CLZ for SVE, as suggested in PR109498. The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression. OK for mainline? Signed-off-by: Soumya AR <soum...@nvidia.com> gcc/ChangeLog: PR target/109498 * config/aarch64/aarch64-sve.md (ctz<mode>2): Added pattern to expand CTZ to RBIT + CLZ for SVE. gcc/testsuite/ChangeLog: PR target/109498 * gcc.target/aarch64/sve/ctz.c: New test.
