https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212

--- Comment #381 from Kazumoto Kojima <kkojima at gcc dot gnu.org> ---
(In reply to John Paul Adrian Glaubitz from comment #378)
> I just tried a full bootstrap using that tree with all languages but Rust
> and Go enabled and it fails with:
> 
> during RTL pass: subreg3
> ../../gcc/ipa-sra.cc: In function 'void
> {anonymous}::isra_read_edge_summary(lto_input_block*, cgraph_edge*)':
> ../../gcc/ipa-sra.cc:2933:1: internal compiler error: in
> decompose_multiword_subregs, at lower-subreg.cc:1731

Compression of the huge test case is still in progress.  It seems it happens
for -O2 -fpic for the original test case.  A quick look at an intermediate test
case with gdb shows that the compiler complains

(set (mem:QI (plus:SI (reg:SI 555)
            (reg:SI 0 r0)) [0  S1 A8])
    (subreg:QI (reg:DI 214 [ bp$word ]) 0))

can't be recognized.   I've missed that devel/sh-lra removed the following
patterns

(define_insn "*mov<mode>_store_mem_index"
  [(set (mem:QIHI
                (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
                               (match_operand:SI 1 "arith_reg_operand" "z")))
           (match_operand:QIHI 2 "arith_reg_operand" "r"))]
  "TARGET_SH1 && ! TARGET_SH2A && sh_lra_p ()
   && REG_P (operands[1]) && REGNO (operands[1]) == R0_REG"
  "mov.<bw>     %2,@(%1,%0)"
  [(set_attr "type" "store")])

(define_insn "*movsf_ie_store_mem_index"
  [(set (mem:SF
               (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
                              (match_operand:SI 1 "arith_reg_operand" "z")))
           (match_operand:SF 2 "fp_arith_reg_operand" "f"))
    (use (reg:SI FPSCR_MODES_REG))]
  "TARGET_SH2E && sh_lra_p ()
   && REG_P (operands[1]) && REGNO (operands[1]) == R0_REG"
  "fmov.s    %2,@(%1,%0)"
  [(set_attr "type" "store")])

(define_insn "*movsf_ie_load_mem_index"
  [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
           (mem:SF
               (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r")
                              (match_operand:SI 2 "arith_reg_operand" "z"))))
   (use (reg:SI FPSCR_MODES_REG))]
  "TARGET_SH2E && sh_lra_p ()
   && REG_P (operands[2]) && REGNO (operands[2]) == R0_REG"
  "fmov.s    @(%2,%1),%0"
  [(set_attr "type" "load")])

required as no-clobber versions of the similar patterns.  The ICE in c#378 is
fixed here with adding the above patterns to devel/sh-lra.

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