https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212
--- Comment #296 from Oleg Endo <olegendo at gcc dot gnu.org> --- (In reply to Kazumoto Kojima from comment #295) > (In reply to Kazumoto Kojima from comment #285) > > (In reply to Oleg Endo from comment #284) > > > (In reply to Kazumoto Kojima from comment #283) > > ... > > > > It turned out that the c#276 version of block_lump_real_i4 works > > > > correctly > > > > in only the limited cases. > > > > > > Have you tried writing the pattern as > > > > > > (define_insn "block_lump_real_i4" > > > [(set (mem:BLK (match_operand:SI 2 "" "r,r")) > > > (mem:BLK (match_operand:SI 3 "" "r,r"))) > > > (use (match_operand:SI 0 "arith_reg_operand" "r,r")) > > > (use (match_operand 1 "" "Z,Ccl")) > > > ... > > > > > > i.e. without the parallel in there? Sorry, maybe it's a stupid idea but > > > ... > > > > The last time I tried it against slightly different patterns, there was no > > difference. I'll try it again. > > It seems that there is no difference w/wo the explicit parallel pattern. > > BTW, a bit monstrous version of that pattern seems to work at least for gcc > testsuite and our handy test case: > > (define_insn "block_lump_real_i4" > [(set (mem:BLK (match_operand:SI 2 "" "=r,r")) > (mem:BLK (match_operand:SI 3 "" "=r,r"))) > (use (match_operand:SI 0 "arith_reg_operand" "r,r")) > (use (match_operand 1 "" "Z,Ccl")) > (use (match_operand:SI 4 "" "=r,r")) > (use (reg:SI R4_REG)) > (use (reg:SI R5_REG)) > (use (reg:SI R6_REG)) > (clobber (match_dup 2)) > (clobber (match_dup 3)) > (clobber (match_dup 4)) > (clobber (reg:SI PR_REG)) > (clobber (reg:SI T_REG)) > (clobber (reg:SI R0_REG)) > (clobber (reg:SI R1_REG)) > (clobber (reg:SI R2_REG)) > (clobber (reg:SI R3_REG))] > "TARGET_HARD_SH4 > && REG_P (operands[2]) && REGNO (operands[2]) == R4_REG > && REG_P (operands[3]) && REGNO (operands[3]) == R5_REG > && REG_P (operands[4]) && REGNO (operands[4]) == R6_REG" > "@ > jsr @%0%# > bsrf %0\n%O1:%#" > [(set_attr "type" "sfunc") > (set_attr "needs_delay_slot" "yes")]) > > The extra use patterns avoid allocating R4-R6 to operands[0]. This sounds almost logical and easy to understand. > Adding explicit emit_clobber R4-R6 looks better than this to me, though. Having to use the "emit_clobber" when instantiating that pattern might be easy to forget. It's easier to deal with it when it's all contained in one place. Ideally a single 'emit_insn' should suffice, IMHO. > && REG_P (operands[2]) && REGNO (operands[2]) == R4_REG > && REG_P (operands[3]) && REGNO (operands[3]) == R5_REG > && REG_P (operands[4]) && REGNO (operands[4]) == R6_REG" Out of curiousity, why are these checks needed?
