https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89213
--- Comment #9 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Michael Meissner <meiss...@gcc.gnu.org>: https://gcc.gnu.org/g:9a07ac151327f61963b092062eb8566dd0c6f0cd commit r15-3676-g9a07ac151327f61963b092062eb8566dd0c6f0cd Author: Michael Meissner <meiss...@linux.ibm.com> Date: Tue Sep 17 21:05:27 2024 -0400 PR 89213: Add better support for shifting vectors with 64-bit elements This patch fixes PR target/89213 to allow better code to be generated to do constant shifts of V2DI/V2DF vectors. Previously GCC would do constant shifts of vectors with 64-bit elements by using: XXSPLTIB 32,4 VEXTSB2D 0,0 VSRAD 2,2,0 I.e., the PowerPC does not have a VSPLTISD instruction to load -15..14 for the 64-bit shift count in one instruction. Instead, it would need to load a byte and then convert it to 64-bit. With this patch, GCC now realizes that the vector shift instructions will look at the bottom 6 bits for the shift count, and it can use either a VSPLTISW or XXSPLTIB instruction to load the shift count. 2024-09-17 Michael Meissner <meiss...@linux.ibm.com> gcc/ PR target/89213 * config/rs6000/altivec.md (UNSPEC_VECTOR_SHIFT): New unspec. (VSHIFT_MODE): New mode iterator. (vshift_code): New code iterator. (vshift_attr): New code attribute. (altivec_<mode>_<vshift_attr>_const): New pattern to optimize vector long long/int shifts by a constant. (altivec_<mode>_shift_const): New helper insn to load up a constant used by the shift operation. * config/rs6000/predicates.md (vector_shift_constant): New predicate. gcc/testsuite/ PR target/89213 * gcc.target/powerpc/pr89213.c: New test. * gcc.target/powerpc/vec-rlmi-rlnm.c: Update instruction count.
