[Bug target/116592] illegal operands th.vsetvli zero,0,e32,m8 with -O2 -O3 when compiling for risc-v xtheadvector

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116592

--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <l...@gcc.gnu.org>:

https://gcc.gnu.org/g:d620499b3a24f14cfb98529640584e63d7eca149

commit r15-3527-gd620499b3a24f14cfb98529640584e63d7eca149
Author: Jin Ma <ji...@linux.alibaba.com>
Date:   Sat Sep 7 10:29:02 2024 -0600

    [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli
zero,0,e32,m8" for XTheadVector

    Since the THeadVector vsetvli does not support vl as an immediate, we
    need to convert 0 to zero when outputting asm.

            PR target/116592

    gcc/ChangeLog:

            * config/riscv/thead.cc (th_asm_output_opcode): Change '0' to
            "zero"

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/xtheadvector/pr116592.c: New test.