https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212
--- Comment #233 from Kazumoto Kojima <kkojima at gcc dot gnu.org> --- Created attachment 59062 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59062&action=edit a patch to fix other ICEs during libada build The second one is the ICE in split2 pass during building libada with the unrecognizable insn: (insn 1695 103 1694 12 (set (reg:SF 150 fpul) (reg:SF 150 fpul)) "s-valrea.adb":157:13 -1 (nil)) which looks to be generated with (define_split [(set (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "register_operand" "")) (use (reg:SI FPSCR_MODES_REG)) (clobber (reg:SI FPUL_REG))] "TARGET_SH1" [(parallel [(set (reg:SF FPUL_REG) (match_dup 1)) (use (reg:SI FPSCR_MODES_REG)) (clobber (scratch:SI))]) (parallel [(set (match_dup 0) (reg:SF FPUL_REG)) (use (reg:SI FPSCR_MODES_REG)) (clobber (scratch:SI))])] "") when operand 1 is FPUL itself. movsf_ie_ra could make that pattern which was never generated with the old RA. It went away with adding guards so not to permit this splitting when fpul is given as the operand 0/1. There is another ICE for the unrecognizable insn: (insn 5 307 288 (parallel [ (set (reg/v:SF 2 r2 [orig:167 s ] [167]) (mem/u/c:SF (label_ref 521) [0 S4 A32])) (use (reg:SI 154 fpscr0)) (clobber (mem/c:SI (plus:SI (reg:SI 2 r2 [306]) (const_int 60 [0x3c])) [29 %sfp+-4 S4 A32])) ]) "s-valrea.adb":358:12 -1 (nil)) during mach pass. Looks LRA allocates mem for the scratch pattern of movsf_ie (clobber (match_scratch:SI 2 "=...&z...")) of which constraint is early clobbered r0. Looks an LRA specific auxiliary movsf pattern for constant load works as a workaround. The patches are not tested well and can cause new issues. Tested only target libgcc/libstdc++v3/libada build with -O2 -m4 -mlra.
