https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114063
ktkachov at gcc dot gnu.org changed:
What |Removed |Added
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CC| |ktkachov at gcc dot gnu.org
Last reconfirmed|2024-02-22 00:00:00 |2024-8-28
--- Comment #2 from ktkachov at gcc dot gnu.org ---
I looked into this a bit. A couple things are preventing this currently:
The check_war_ptrs expander in aarch64-sve2.md requires that the accesses
length is exactly the size of an SVE vector.
In the -march=armv9-a case that's a poly-int [16, 16] and is accepted by
aarch64_bytes_per_sve_vector_operand.
For -mcpu=neoverse-v2 this is a const_int 32 and thus rejected.
It is 32 because of the use of Advanced SIMD and 2x unrolling.
If we compile the testcase with --param=aarch64-vect-unroll-limit=1
-msve-vector-bits=128 then the whilewr is generated even with an Advanced SIMD
main loop
