https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115948
Bug ID: 115948
Summary: [SH] wrong fpu mode-switch
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: olegendo at gcc dot gnu.org
Target Milestone: ---
Created attachment 58677
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58677&action=edit
reduced reproducer
The attached reproducer, compiled on sh-elf with 'sh-elf-gcc -S -O2 -m4 -ml'
will produce wrong-code around one of the function calls.
It contains a sequence:
lds r1,fpscr ! 71 [c=0 l=2] lds_fpscr/0
mov.l .L5,r8 ! 6 [c=10 l=2] movsi_ie/0
mov #0,r4 ! 8 [c=4 l=2] movsi_ie/2
xor r2,r1 ! 74 [c=4 l=2] xorsi3/1
fldi1 fr5 ! 7 [c=10 l=2] movsf_ie/3
lds r1,fpscr ! 75 [c=0 l=2] lds_fpscr/0
jsr @r8
nop ! 9 [c=0 l=4] calli
which is the (inefficient but) correct way of using 'fldi1' when the fpu is in
double-mode.
However, a few function calls later, it forgets to emit the mode-switch change:
fldi1 fr5 ! 32 [c=10 l=2] movsf_ie/3
jsr @r8 ! 34 [c=0 l=2] calli
mov #0,r4 ! 33 [c=4 l=2] movsi_ie/2
which results in an illegal instruction trap, since 'fldi1' is not defined for
the case when the fpu is in double-mode.
