[Bug target/115922] New: Missed optimization: MIPS: clear bit 15

[lis8215 at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115922

            Bug ID: 115922
           Summary: Missed optimization: MIPS: clear bit 15
           Product: gcc
           Version: 15.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: lis8215 at gmail dot com
  Target Milestone: ---

Created attachment 58659
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58659&action=edit
silly patch designed for mips32 mips32r2

simple testcase:
# define MASK (~(0x8000U))

host_width_type_t test(host_width_type_t x)
{
    return x & MASK;
}

Now for clearing bit 15 GCC emits something like:
test:
        li      $2,-65536    # 0xffff0000
        addiu   $2,$2,32767  # 0xffff7fff
        and     $2,$4,$2

while it's cheaper to use:
        ori     $2,$2,32768  #0x8000
        xori    $2,$2,32768

any mask in range ~0x8000 .. ~0xfffe seems profitable, even for MIPS32r2+
where INS instruction can be used to clear group of bits.

Such pattern appears rarely and mostly in low level software e.g. linux kernel.
for linux kernel it shows ~40 matches per million of insns.

Might also be profitable for RISC-V, not tested.