[Bug target/115611] mve: vsetq_lane for 64-bits has wrong codegen when setting lane 1

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115611

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-14 branch has been updated by Andre Simoes Dias Vieira
<avie...@gcc.gnu.org>:

https://gcc.gnu.org/g:b7a16ad1df8b00e084ef6bf0c23e5f8bdc5f419b

commit r14-10408-gb7a16ad1df8b00e084ef6bf0c23e5f8bdc5f419b
Author: Andre Vieira <andre.simoesdiasvie...@arm.com>
Date:   Thu Jul 11 15:38:45 2024 +0100

    mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

    This patch fixes the backend pattern that was printing the wrong input
    scalar register pair when inserting into lane 1.

    Added a new test to force float-abi=hard so we can use scan-assembler to
check
    correct codegen.

    gcc/ChangeLog:

            PR target/115611
            * config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of
input
            scalar register pair when lane = 1.

    gcc/testsuite/ChangeLog:

            * gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.

    (cherry picked from commit 7c11fdd2cc11a7058e9643b6abf27831970ad2c9)