[Bug target/115725] RISC-V: Use wrong AVL for rv64gcv_zfh_zvl512b

[pan2.li at intel dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115725

--- Comment #6 from Li Pan <pan2.li at intel dot com> ---
(In reply to Robin Dapp from comment #5)
> > zvl128b => GOOD.
> > vec_set_vnx8hi_0:
> >         vl1re16.v       v1,0(a1)
> >         vsetivli        zero,1,e16,m1,ta,ma
> >         vmv.s.x v1,a2
> >         vs1r.v  v1,0(a0)  // Only store 1 element as source code.
> >         ret
> > 
> > 
> > zvl512b => BAD.
> > vec_set_vnx8hi_0:
> >         vsetivli        zero,1,e16,mf4,ta,ma
> >         vle16.v v1,0(a1)
> >         vmv.s.x v1,a2
> >         vsetivli        zero,8,e16,mf4,ta,ma
> >         vse16.v v1,0(a0) // Store 8 elements
> >         ret
> 
> Isn't this similar in that both write a "full" 8-element vector?

Oh, yes, you are right, missed the vs1r whole register store which doesn't
honor vl.