https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105733
--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Vineet Gupta <vine...@gcc.gnu.org>: https://gcc.gnu.org/g:f9cfc192ed0127edb7e79818917dd2859fce4d44 commit r15-757-gf9cfc192ed0127edb7e79818917dd2859fce4d44 Author: Vineet Gupta <vine...@rivosinc.com> Date: Mon May 13 11:46:03 2024 -0700 RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] If the constant used for stack offset can be expressed as sum of two S12 values, the constant need not be materialized (in a reg) and instead the two S12 bits can be added to instructions involved with frame pointer. This avoids burning a register and more importantly can often get down to be 2 insn vs. 3. The prev patches to generally avoid LUI based const materialization didn't fix this PR and need this directed fix in funcion prologue/epilogue expansion. This fix doesn't move the neddle for SPEC, at all, but it is still a win considering gcc generates one insn fewer than llvm for the test ;-) gcc-13.1 release | gcc 230823 | | | g6619b3d4c15c | This patch | clang/llvm --------------------------------------------------------------------------------- li t0,-4096 | li t0,-4096 | addi sp,sp,-2048 | addi sp,sp,-2048 addi t0,t0,2016 | addi t0,t0,2032 | add sp,sp,-16 | addi sp,sp,-32 li a4,4096 | add sp,sp,t0 | add a5,sp,a0 | add a1,sp,16 add sp,sp,t0 | addi a5,sp,-2032 | sb zero,0(a5) | add a0,a0,a1 li a5,-4096 | add a0,a5,a0 | addi sp,sp,2032 | sb zero,0(a0) addi a4,a4,-2032 | li t0, 4096 | addi sp,sp,32 | addi sp,sp,2032 add a4,a4,a5 | sb zero,2032(a0) | ret | addi sp,sp,48 addi a5,sp,16 | addi t0,t0,-2032 | | ret add a5,a4,a5 | add sp,sp,t0 | add a0,a5,a0 | ret | li t0,4096 | sd a5,8(sp) | sb zero,2032(a0)| addi t0,t0,-2016 | add sp,sp,t0 | ret | gcc/ChangeLog: PR target/105733 * config/riscv/riscv.h: New macros for with aligned offsets. * config/riscv/riscv.cc (riscv_split_sum_of_two_s12): New function to split a sum of two s12 values into constituents. (riscv_expand_prologue): Handle offset being sum of two S12. (riscv_expand_epilogue): Ditto. * config/riscv/riscv-protos.h (riscv_split_sum_of_two_s12): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr105733.c: New Test. * gcc.target/riscv/rvv/autovec/vls/spill-1.c: Adjust to not expect LUI 4096. * gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-7.c: Ditto. Tested-by: Edwin Lu <e...@rivosinc.com> # pre-commit-CI #1568 Signed-off-by: Vineet Gupta <vine...@rivosinc.com>
