[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[ubizjak at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #11 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Jakub Jelinek from comment #8)
> (In reply to Uroš Bizjak from comment #7)
> > (define_insn_and_split "*andn<dwi>3_doubleword_bmi"
> >   [(set (match_operand:<DWI> 0 "register_operand" "=&r,r,r")
> >     (and:<DWI>
> >       (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r,0,r"))
> >       (match_operand:<DWI> 2 "nonimmediate_operand" "ro,ro,0")))
> >    (clobber (reg:CC FLAGS_REG))]
> > 
> > where the problematic alternative (=&r,r,ro) allows a memory input in its
> > operand 2 constraint. The allocator could spill a DImode value to a stack in
> > advance and reload the value from the memory in this particular alternative.
> 
> So, given the known ia32 register starvation, can't we split that first
> alternative to
> =&r,r,o with "nox64" isa and =&r,r,ro with "x64" isa?

Yes, IMO this is an acceptable workaround, but please split the constraint to
(=&r,r,r) and (=&r,r,o), with the former limited to "x64" isa. This is what the
other patterns do, new mode attribute just hides the obvious fact.