[Bug target/114668] [14] RISC-V rv64gcv: miscompile at -O3

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114668

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Looks to be working on aarch64 (both with/without SVE):
```
[apinski@xeond2 upstream-cross-aarch64]$ ./install/bin/aarch64-linux-gnu-gcc
-O3 -fno-vect-cost-model t6.c -static -fno-vect-cost-model
[apinski@xeond2 upstream-cross-aarch64]$ ./install-qemu/bin/qemu-aarch64 a.out
1
1
[apinski@xeond2 upstream-cross-aarch64]$ ./install/bin/aarch64-linux-gnu-gcc
-O3 -fno-vect-cost-model t6.c -static -march=armv9-a+sve -fno-vect-cost-model
[apinski@xeond2 upstream-cross-aarch64]$ ./install-qemu/bin/qemu-aarch64 a.out
1
1

```