https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114288
--- Comment #5 from John David Anglin <danglin at gcc dot gnu.org> ---
This is what we have from reload with Sam's reduced test case:
(insn 9 103 123 2 (set (reg/f:SI 1 %r1)
(plus:SI (reg:SI 19 %r19)
(high:SI (symbol_ref:SI ("indirect_child") <var_decl 0xf78e81b8
indirect_child>)))) "beta.c":18:32 53 {*pa.md:2656}
(nil))
(insn 123 9 11 2 (set (reg:SI 20 %r20 [113])
(reg/f:SI 1 %r1)) "beta.c":18:32 42 {*pa.md:2195}
(nil))
(insn 11 123 10 2 (set (reg:SI 1 %r1 [115])
(plus:SI (reg:SI 19 %r19)
(high:SI (symbol_ref/u:SI ("*.LC0") [flags 0x2])))) "beta.c":18:32
53 {*pa.md:2656}
(nil))
(note 10 11 12 2 NOTE_INSN_DELETED)
(insn 12 10 13 2 (set (reg/f:SI 20 %r20 [114])
(mem/u/c:SI (lo_sum:SI (reg:SI 1 %r1 [115])
(unspec:SI [
(symbol_ref/u:SI ("*.LC0") [flags 0x2])
] UNSPEC_DLTIND14R)) [0 S4 A32])) "beta.c":18:32 42
{*pa.md:2195}
(expr_list:REG_EQUIV (symbol_ref/u:SI ("*.LC0") [flags 0x2])
(nil)))
(insn 13 12 125 2 (set (reg:DF 68 %fr22 [116])
(mem/u/c:DF (reg/f:SI 20 %r20 [114]) [0 S8 A64])) "beta.c":18:32 75
{*pa.md:3866}
(expr_list:REG_EQUIV (mem/c:DF (plus:SI (reg/f:SI 146)
(const_int 16 [0x10])) [1 indirect_child.cg.prop.fract+0 S8
A64])
(nil)))
(insn 125 13 127 2 (set (reg:SI 20 %r20)
(const_int 32 [0x20])) "beta.c":18:32 42 {*pa.md:2195}
(nil))
(insn 127 125 128 2 (set (reg:SI 20 %r20)
(reg/f:SI 146)) "beta.c":18:32 42 {*pa.md:2195}
(nil))
(insn 128 127 14 2 (set (reg:SI 20 %r20)
(plus:SI (reg:SI 20 %r20)
(const_int 32 [0x20]))) "beta.c":18:32 120 {addsi3}
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 146)
(const_int 32 [0x20]))
(nil)))
(insn 14 128 116 2 (set (mem/c:DF (plus:SI (reg:SI 20 %r20)
(const_int -16 [0xfffffffffffffff0])) [1
indirect_child.cg.prop.fract+0 S8 A64])
(reg:DF 68 %fr22 [116])) "beta.c":18:32 75 {*pa.md:3866}
(nil))
In ira, we had:
(insn 9 103 11 2 (set (reg:SI 113)
(plus:SI (reg:SI 19 %r19)
(high:SI (symbol_ref:SI ("indirect_child") <var_decl 0xf78e81b8
indirect_child>)))) "beta.c":18:32 53 {*pa.md:2656}
(nil))
(insn 11 9 10 2 (set (reg:SI 115)
(plus:SI (reg:SI 19 %r19)
(high:SI (symbol_ref/u:SI ("*.LC0") [flags 0x2])))) "beta.c":18:32
53 {*pa.md:2656}
(nil))
(insn 10 11 12 2 (set (reg/f:SI 146)
(mem/u/c:SI (lo_sum:SI (reg:SI 113)
(unspec:SI [
(symbol_ref:SI ("indirect_child") <var_decl 0xf78e81b8
indirect_child>)
] UNSPEC_DLTIND14R)) [0 S4 A32])) "beta.c":18:32 42
{*pa.md:2195}
(expr_list:REG_DEAD (reg:SI 113)
(expr_list:REG_EQUIV (symbol_ref:SI ("indirect_child") <var_decl
0xf78e81b8 indirect_child>)
(nil))))
(insn 12 10 13 2 (set (reg/f:SI 114)
(mem/u/c:SI (lo_sum:SI (reg:SI 115)
(unspec:SI [
(symbol_ref/u:SI ("*.LC0") [flags 0x2])
] UNSPEC_DLTIND14R)) [0 S4 A32])) "beta.c":18:32 42
{*pa.md:2195}
(expr_list:REG_DEAD (reg:SI 115)
(expr_list:REG_EQUIV (symbol_ref/u:SI ("*.LC0") [flags 0x2])
(nil))))
(insn 13 12 14 2 (set (reg:DF 116)
(mem/u/c:DF (reg/f:SI 114) [0 S8 A64])) "beta.c":18:32 75
{*pa.md:3866}
(expr_list:REG_DEAD (reg/f:SI 114)
(expr_list:REG_EQUIV (mem/c:DF (plus:SI (reg/f:SI 146)
(const_int 16 [0x10])) [1 indirect_child.cg.prop.fract+0 S8
A64])
(nil))))
(insn 14 13 110 2 (set (mem/c:DF (plus:SI (reg/f:SI 146)
(const_int 16 [0x10])) [1 indirect_child.cg.prop.fract+0 S8
A64])
(reg:DF 116)) "beta.c":18:32 75 {*pa.md:3866}
(expr_list:REG_DEAD (reg:DF 116)
(nil)))
