https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100165
--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> --- For the ones which produce ins, it should be easy to modify the pattern to emit fmov for those cases, that is `elt == 0`: (define_insn "aarch64_simd_vec_set_zero<mode>" [(set (match_operand:VALLS_F16 0 "register_operand" "=w") (vec_merge:VALLS_F16 (match_operand:VALLS_F16 1 "aarch64_simd_imm_zero" "") (match_operand:VALLS_F16 3 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0" { int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2]))); operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); return "ins\\t%0.<Vetype>[%p2], <vwcore>zr"; } )