https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113682
--- Comment #5 from Mathias Stearn <redbeard0531 at gmail dot com> --- (In reply to Andrew Pinski from comment #2) > I should note that on x86, 2 cmov in a row might be an issue and worse than > branches. There is a cost model and the x86 backend rejects that. > > There are some cores where it is worse. I don't know if it applies to recent > ones though. Do you know if that applies to any cores that support x86_64? I checked Agner Fog's tables, and only very very old cores (P4 era) had high reciprocal throughput, but even then it was less than latency. It looks like all AMD cores and intel cores newer than ivy bridge (ie everything from the last 10 years) are able to execute multiple CMOVs per cycle (reciprocal throughput < 1). From what I can see, it looks like bad CMOV was a particular problem of the Pentium 4 and Prescott cores, and possibly PPro, but I don't see the numbers for it. I don't think any of those cores should have an impact on the default cost model in 2024.
