[Bug target/113429] RISC-V: SPEC2017 527 cam4 miscompilation in autovec VLA build

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113429

--- Comment #12 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Patrick O'Neill <pone...@gcc.gnu.org>:

https://gcc.gnu.org/g:7f7d9c525c694e36ae525ed93ccd5b6ffad0f1d8

commit r14-8379-g7f7d9c525c694e36ae525ed93ccd5b6ffad0f1d8
Author: Patrick O'Neill <patr...@rivosinc.com>
Date:   Tue Jan 23 16:36:53 2024 -0800

    RISC-V: Add regression test for vsetvl bug pr113429

    The reduced testcase for pr113429 (cam4 failure) needed additional
    modules so it wasn't committed.
    The fuzzer found a c testcase that was also fixed with pr113429's fix.
    Adding it as a regression test.

            PR target/113429

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/vsetvl/pr113429.c: New test.

    Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>