https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773
--- Comment #14 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Robin Dapp <rd...@gcc.gnu.org>: https://gcc.gnu.org/g:0a5170b5f596bb5fcedf25d93952b979d02d1f56 commit r14-6555-g0a5170b5f596bb5fcedf25d93952b979d02d1f56 Author: Robin Dapp <rd...@ventanamicro.com> Date: Sun Dec 3 21:55:16 2023 +0100 expmed: Use GET_MODE_PRECISION and expander's output mode. This changes the vec_extract path of extract_bit_field to use GET_MODE_PRECISION instead of GET_MODE_BITSIZE and uses the mode obtained from insn_data[icode].operand[0] as target mode. Also, it adds a vec_extract<mode>bi expander for riscv that maps to vec_extract<mode>qi. This fixes an ICE on riscv where we did not find a vec_extract optab and continued with the generic code which requires 1-byte alignment that riscv mask modes do not provide. Apart from that it adds poly_int support to riscv's vec_extract expander and makes the RVV..BImode -> QImode expander call emit_vec_extract in order not to duplicate code. gcc/ChangeLog: PR target/112773 * config/riscv/autovec.md (vec_extract<mode>bi): New expander calling vec_extract<mode>qi. * config/riscv/riscv-protos.h (riscv_legitimize_poly_move): Export. (emit_vec_extract): Change argument from poly_int64 to rtx. * config/riscv/riscv-v.cc (shuffle_extract_and_slide1up_patterns): Ditto. * config/riscv/riscv.cc (riscv_legitimize_poly_move): Export. (riscv_legitimize_move): Use rtx instead of poly_int64. * expmed.cc (store_bit_field_1): Change BITSIZE to PRECISION. (extract_bit_field_1): Change BITSIZE to PRECISION and use return mode from insn_data as target mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/pr112773.c: New test.
