https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111867
--- Comment #10 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The trunk branch has been updated by Andrew Pinski <pins...@gcc.gnu.org>: https://gcc.gnu.org/g:35ade856eaafd9c39ce864b25d127e1f98a3bb57 commit r14-6421-g35ade856eaafd9c39ce864b25d127e1f98a3bb57 Author: Andrew Pinski <quic_apin...@quicinc.com> Date: Sat Dec 9 20:02:24 2023 -0800 aarch64: Fix wrong code for bfloat when f16 is enabled [PR 111867] The problem here is when f16 is enabled, movbf_aarch64 accepts `Ufc` as a constraint: [ w , Ufc ; fconsts , fp16 ] fmov\t%h0, %1 But that is for fmov values and in this case fmov represents f16 rather than bfloat16 values. This means we would get the wrong value in the register. Built and tested for aarch64-linux-gnu with no regressions. Also tested with `-march=armv9-a+sve2, gcc.dg/torture/bfloat16-basic.c and gcc.dg/torture/bfloat16-builtin.c no longer fail. gcc/ChangeLog: PR target/111867 * config/aarch64/aarch64.cc (aarch64_float_const_representable_p): For BFmode, only accept +0.0. Signed-off-by: Andrew Pinski <quic_apin...@quicinc.com>
