[Bug middle-end/112872] [14 Regression] RISCV ICE: in store_integral_bit_field, at expmed.cc:1049 with -03 rv64gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112872

--- Comment #2 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Thanks.  Yes that's similar and also looks fixed by the introduction of the
vec_init expander.  Added this test case to the patch and will push it soon.