https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112598
--- Comment #14 from Li Pan <pan2.li at intel dot com> --- The below diff similar to the x86 workaround looks not working, unless we change the `+m` to `=m`. But I don't fully test the impact of this change except the case itself. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 935eeb7fd8e..882fc8fe5ec 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -85,6 +85,9 @@ (define_c_enum "unspec" [ ;; String unspecs UNSPEC_STRLEN + + ;; test + UNSPEC_MASKSTORE ]) (define_c_enum "unspecv" [ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index ba9c9e5a9b6..2f74cec51d1 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1738,16 +1738,17 @@ (define_insn_and_split "*pred_mov<mode>" ;; Dedicated pattern for vse.v instruction since we can't reuse pred_mov pattern to include ;; memory operand as input which will produce inferior codegen. (define_insn "@pred_store<mode>" - [(set (match_operand:V 0 "memory_operand" "+m") - (if_then_else:V - (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1") - (match_operand 3 "vector_length_operand" " rK") - (match_operand 4 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:V 2 "register_operand" " vr") - (match_dup 0)))] + [(set (match_operand:V 0 "memory_operand" "=m") + (unspec:V + [(if_then_else:V + (unspec:<VM> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1") + (match_operand 3 "vector_length_operand" " rK") + (match_operand 4 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (match_operand:V 2 "register_operand" " vr") + (match_dup 0))] UNSPEC_MASKSTORE))] "TARGET_VECTOR" "vse<sew>.v\t%2,%0%p1" [(set_attr "type" "vste")
