https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112092
--- Comment #3 from Maciej W. Rozycki <macro at orcam dot me.uk> ---
Maybe I'm missing something, but the RVV spec has this for VSETVLI:
"The application specifies the total number of elements to be processed
(the application vector length or AVL) as a candidate value for vl, and
the hardware responds via a general-purpose register with the (frequently
smaller) number of elements that the hardware will handle per iteration
(stored in vl), based on the microarchitectural implementation and the
vtype setting."
Is is guaranteed by the RVV specification that the value of `vl' produced
(which is then supplied as an argument to `__riscv_vle32_v_i32m1', etc.;
I presume implicitly via the VL CSR as I can't see it in actual assembly
produced) is going to be the same for all microarchitectures for both:
vsetvli zero,a6,e32,m1,tu,ma
and:
vsetvli zero,a6,e16,mf2,ta,ma
?
If it is, then still the code is awkward and the conditional ought to be
removed and the code paths merged as both legs execute the same
instruction.
What is the definition of the `vl' parameter to `__riscv_vle32_v_i32m1',
etc. anyway? I have troubles chasing one down and the source code is so
convoluted with macros I can't even find the implementation.
