[Bug target/111947] RISC-V vector: RTL Check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Lehua Ding <lh...@gcc.gnu.org>:

https://gcc.gnu.org/g:7b2984ad76cac67b962eeb39eab62b6dacf7845e

commit r14-4876-g7b2984ad76cac67b962eeb39eab62b6dacf7845e
Author: Juzhe-Zhong <juzhe.zh...@rivai.ai>
Date:   Tue Oct 24 10:12:49 2023 +0800

    RISC-V: Fix ICE of RTL CHECK on VSETVL PASS[PR111947]

    ICE on vsetvli a5, 8 instruction demand info.

    The AVL is const_int 8 which ICE on RENGO caller.

    Committed as it is obvious fix.

            PR target/111947

    gcc/ChangeLog:

            * config/riscv/riscv-vsetvl.cc
(pre_vsetvl::compute_lcm_local_properties): Add REGNO check.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/vsetvl/pr111947.c: New test.